The present application relates generally to semiconductor devices and includes methods and structures for improving the fabrication of semiconductor devices such as 3D memory structures.
In the fabrication of semiconductor devices, different structures are placed in proximity to each other in the formation of a finished device. For example, a 3D memory structure may include peripheral circuitry and array circuitry. The varying conditions required for the formation of the different structures can cause adverse affects to other structures.
As an example, the array region may be located in a trench provided in a substrate. The formation of such a trench, for example by reactive ion etching, can cause a loading effect that increases process variations and impacts device yield.
As another example, the array region and peripheral region (or varying aspects thereof), may require exposure to significant temperatures for non-negligible periods of time in their formation. This exposure can negatively affect or otherwise cause damage to structures already formed on the device. This concept may be referred to as a thermal budget. Exceeding such a thermal budget for already formed portions of the device can cause damage and impact device yield.
There is a need for improved processes and structures, particularly in the case of 3D memory devices but also for other devices, to reduce the use of process steps that may cause damage to already formed structures and to reduce the likelihood of thermal damage to already formed structures.